Home >> March 2012 Edition >> Insight: How To Lose Weight The *All Digital* Way...
Insight: How To Lose Weight The *All Digital* Way...
by Allan Chin and Luciano Zoso, Stellamar

Programmable digital devices, led by FPGAs, have exploded in popularity for aerospace applications. Major advances in performance and radiation tolerance/hardness have fueled the growth. This also leads to an increase in FPGA usage in other high-reliability and system-critical applications. A recent article in the EE Times, Programmable ICs: The Next Innovation Engine, identifies and describes the most fundamental challenges to continuing the growth path of FPGAs in these applications. Challenge number one in this article is mixed signal circuit integration. Specifically, the article mentions that ADCs, DACs and power circuits will need to be integrated to drive the next wave of FPGA evolution.

stellamarGrph1 Analog design, especially for space, is a highly complicated task requiring tremendous resources, both in terms of time and dollars. This is why there are a limited number of space qualified external analog components. The options are usually targeted at the most advanced speeds, and cost a pretty penny, and also represent points of failure. Most of these parts are not optimal for general sensor applications. General current and temperature “housekeeping” measurements offer all sorts of advantages during a mission. But, take for example, the absurdity of measuring your system’s current temperature with a 4 channel 12 bit, 1msps ADC. This is like trying to drive the head of a pin with a sledgehammer.

An A2D Without The "A"
At Stellamar, All Digital ADC IP core requires no analog block design. Only a few passive components are necessary. Specialized proprietary signal processing enables analog sigma-delta ADC performance to be replicated with all digital library cells. This proprietary technology allows digital ADCs to reap all the benefits that digital design has over analog designed external parts:

50 percent lower power on average
68 percent smaller area on average
Process technology independence
Reduced risk and cycle time
Digital integration and synthesis
Easier radiation-hardened design

These simple block diagrams (Figure 1 and Figure 2) represent some differences.

stellamarfig1 In the traditional analog ADC approach, the designer must select an external ADC part to use an ADC with FPGAs. The bad news is that these ADCs are usually external and large. Multiple pins are needed to connect to an FPGA. By not controlling the ADC development, designers tradeoff optimization for reduced design cycles. The vendor’s solution is most likely an overdesigned part for the system costing power, size and weight. This tradeoff is suboptimal when designing for aerospace and other high reliability applications where reliability is key and costs grow exponentially.

With the All Digital approach, a designer does not have to use external ADCs, which can take up critical board space. The IP core is instantiated right in the FPGA and is much easier to implement through digital synthesis. The digital ADC only uses two pins and a couple discrete components, depicted in Figure 2. Now you have an ADC embedded in the digital fabric of your FPGA, which is properly optimized for your application, and you have also reduced board space, complexity and testing time, while increasing mean time between failures (MTBF). This approach is much easier to implement and test, which can greatly enhance your ability to meet time-to-market. (See Figure 2.)

stellamarfig2 For additional ADC functionality in the conventional approach, either more ADC chips would be added, or an analog multiplexer would have to be added. With the All Digital ADC solution, a designer could just add more digital ADC IP blocks to take advantage of size and power savings.

Figure 3 and Figure 4 are typical frequency response plots for an ADC with a bandwidth of 20 kHz. The plots show an output with two different amplitudes of a 15 kHz input frequency. The first has an amplitude of 1.8 Vpp while the second is 60 dB lower, with an amplitude of 1.8 mVpp.

Performance + Applications
Current performance of this All Digital Solution is up to 14 bits of resolution and 100 kHz bandwidth. Bandwidth depends on the selected resolution. Development efforts continue to support higher performance. Current performance is suitable for a host of space applications including the following:

Sensors—temperature, pressure, voltage, current, acceleration
Touch screen integration
Voice and high quality voice
Motor control

stellamarfig3_4 Implementation Example
Through FPGA partners Xilinx and Microsemi, several customers have used Digital ADC IP cores from Stellamar to provide ADC functionality in aerospace designs. Often “system health monitoring”-sensing of on board current and temperature is forgone because the addition of this capability is too expensive. Digital ADCs are perfect for this application, and allow flight units to be health monitored and debugged on the ground through matching boards. Two examples are:

SEAKR Engineering: On Board Processor Program
Finnish Meteorological Institute: Lunar Landing Mission

Both programs found housekeeping to be an essential feature, but had not found an effective way of implementing without major tradeoffs. In each example, Stellamar helped define requirements, and delivered an IP core customized to the application including number of channels, resolution bandwidth and clock. Total design process is about two weeks. With an All Digital ADC, these teams are able to reduce board space, weight and power and increase reliability.

Radiation Hardening
Since the design of radiation-hardened ADCs is extremely difficult, expensive and lengthy (typically over two years), only few radiation-hardened ADCs are developed that target the applications requiring the highest conversion speed. The same ADCs are used as well for lower speed applications, such as voltage measurements and pressure/acceleration sensors on the system. This means that power is being wasted and system performance is not optimized. If you have a Microsemi radiation-tolerant ProASIC®3 device, or Xilinx V5 QV (for example) already on the board, why not use the remaining 1 percent of the gates to run an optimized digital core which provides an ADC as hard as the surrounding FPGA? Furthermore, Rad Hard ASICs and Structured Arrays such as Honeywell HX5000 can be used in the same way. The Digital ADC is ported to this process and due out in 2012. You have not increased the number of parts, or board space, and now you’re optimized for power, and have a configurable ADC to repurpose for other applications.

RRSat_ad_SM0312 Deliverables
Xilinx and Microsemi-based FPGA evaluation boards are currently available. The intellectual property (IP) retargeted to FPGAs or ASICs is available for purchase. Example performances are 11 bits of resolution over a 20 kHz bandwidth for standard resolution, and 14 bits over 500 Hz for higher resolution applications. A purchased digital ADC block can be specifically optimized just about anywhere below those thresholds. Resolution and sample rates are driven by customer requirements. Stellamar will work with the customer to deliver a customized IP database that best suits those requirements. The IP database will also allow the customer to target desired technology. With the IP database, Stellamar provides a detailed implementation guide, and offers customer support through implementation.

The Digital Solution
Satellite and space electronics designers requiring ADC integration in ASICs or FPGAs now have a simple, flexible and complete solution. With a Stellamar digital ADC, most of the common bottleneck issues caused by ADC integration are removed. The result is a Digital ADC that can be easily embedded in any FPGA, and can be reprogrammed for different performance requirements. This ADC will also be much smaller and less power hungry for low power portable applications and critical aerospace needs. In the near future, engineers will be better able to integrate and synthesize other components previously thought to only remain in the analog domain. The Digital ADC is the first step. Visit http://www.stellamar.com or or email info@stellamar.com for more information.

allanHead About the authors
Allan Chin has more than 30 years of design experience with high performance digital and mixed signal systems. Allan has made significant and recognized accomplishments in the design and engineering of sophisticated electronic systems and assemblies. His broad expertise covers many areas of IC design, including system requirement definition, chip development, mixed signal simulation, verification, prototyping and lab testing. Allan started his career at Honeywell, where he worked on flight and main engine control systems for the space shuttle. Allan also co-developed the digital video encoder chip while at Motorola/Freescale. During his career Allan has held various management positions leading design teams at Motorola/Freescale, Mentor Graphics and Honeywell. Allan has a B.S. in Electrical Engineering from Marquette University, Milwaukee, Wisconsin, and holds nine patents. Allan can be reached at allan.chin@stellamar.com.

lucianoHead Luciano Zoso is an accomplished engineer and inventor with over thirty years of experience in digital signal processing. He has successfully applied his expertise in the areas of voice band modems, sigma-delta converters, multi-standard digital video encoders and decoders, stereo encoders, and GPS receivers as well as sensors. His experience ranges from system-level design and simulation to full implementation. Luciano started his career as a researcher at CSELT, research center of the Italian phone company in Torino, Italy. There he developed advanced data communication systems and pioneered a design methodology for high order sigma-delta converters. After his work at CSELT, Luciano moved to the R&D department of Hayes Microcomputer Products in Atlanta. He then worked with Allan at Motorola/Freescale, where he was responsible for system design of VLSI chips for audio/video and communications applications. There Luciano co-developed the digital video encoder chip with Allan. Luciano is also responsible for the Echo Canceller currently used in landline and satellite communications, and he also created the GPS receiver currently used in cell phones. Luciano has a Dr. Ing Degree in electronics engineering from Politecnico di Torino in Italy. He holds eleven patents in signal processing. Email Luciano at luciano.zoso@stellamar.com.